SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 410

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
EXTS (extend segment) instruction allows switching to a 64 KByte segment oriented
data access scheme for 1...4 instructions without having to change the current DPPs. In
this case all 16 bits of the operand address are used as segment offset, with the segment
taken from the EXTS instruction. This greatly simplifies address calculation with
continuous data like huge arrays in “C”.
EXTS
MOV
MOV
Note: Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC.
Short Addressing in the Extended SFR (ESFR) Space
The short addressing modes of the C161U (REG or BITOFF) implicitly access the SFR
space. The additional ESFR space would have to be accessed via long addressing
modes (MEM or [Rw]). The EXTR (extend register) instruction redirects accesses in
short addressing modes to the ESFR space for 1...4 instructions, so the additional
registers can be accessed this way, too.
EXTPR and EXTSR instructions combine the DPP override mechanism with the
redirection to the ESFR space using a single instruction.
Note: Instructions EXTR, EXTPR and EXTSR inhibit interrupts the same way as
Nested Locked Sequences
Each of the described extension instruction and the ATOMIC instruction starts an
internal “extension counter” counting the effected instructions. When another extension
or ATOMIC instruction is contained in the current locked sequence this counter is
restarted with the value of the new instruction. This allows the construction of locked
sequences longer than 4 instructions.
Note: • Interrupt latencies may be increased when using locked code sequences.
Code Memory Configuration during Reset
The control input pin EA (External Access) enables the user to define the address area
from which the first instructions after reset are fetched. When EA is low (‘0’) during reset,
the internal code memory is disabled and the first instructions are fetched from external
memory. When EA is high (‘1’) during reset, the internal code memory is globally enabled
and the first instructions are fetched from the internal memory.
ATOMIC.
The switching to the ESFR area and data page overriding is checked by the
development tools or handled automatically.
• PEC requests are not serviced during idle mode, if the IDLE instruction is part of
a locked sequence.
#15, #1
R0, [R14]
R1, [R13]
;The override seg. is 15 (0F’0000H..0F’FFFFH)
;The (16-bit) segment offset is stored in R14
;This instruction uses the std. DPP scheme!
410
System Programming
2001-04-19
C161U