SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 49

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

The technique of implementing this circular stack is described in chapter “System
Programming”.
General Purpose Registers
The General Purpose Registers (GPRs) use a block of 16 consecutive words within the
internal RAM. The Context Pointer (CP) register determines the base address of the
currently active register bank. This register bank may consist of up to 16 word GPRs (R0,
R1, ..., R15) and/or of up to 16 byte GPRs (RL0, RH0, ..., RL7, RH7). The sixteen byte
GPRs are mapped onto the first eight word GPRs (see table below).
In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 Byte. The GPRs are accessed via short
2-, 4- or 8-bit addressing modes using the Context Pointer (CP) register as base address
(independent of the current DPP register contents). Additionally, each bit in the currently
active register bank can be accessed individually.
Mapping of General Purpose Registers to RAM Addresses
C161U supports fast register bank (context) switching. Multiple register banks can
physically exist within the internal RAM at the same time. Only the register bank selected
Data Sheet
Internal RAM
Address
<CP> + 1E
<CP> + 1C
<CP> + 1A
<CP> + 18
<CP> + 16
<CP> + 14
<CP> + 12
<CP> + 10
<CP> + 0E
<CP> + 0C
<CP> + 0A
<CP> + 08
<CP> + 06
<CP> + 04
<CP> + 02
<CP> + 00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Byte Registers
---
---
---
---
---
---
---
---
RH7 RL7
RH6 RL6
RH5 RL5
RH4 RL4
RH3 RL3
RH2 RL2
RH1 RL1
RH0 RL0
49
Word Register
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Memory Organization
2001-04-19
C161U