SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 308

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
SSCCON (FFB2
Note: • The target of an access to SSCCON (control bits or flags) is determined by the
The shift register of the SSC is connected to both the transmit pin and the receive pin via
the pin control logic (see block diagram). Transmission and reception of serial data is
synchronized and takes place at the same time, ie. the same number of transmitted bits
is also received. Transmit data is written into the Transmit Buffer SSCTB. It is moved to
the shift register as soon as this is empty. An SSC-master (SSCMS=’1’) immediately
begins transmitting, while an SSC-slave (SSCMS=’0’) will wait for an active shift clock.
When the transfer starts, the busy flag SSCBSY is set and a transmit interrupt request
EN=1
Bit
SSCBC
SSCTE
SSCRE
SSCPE
SSCBE
SSCBSY
SSCMS
SSCEN
SSC
15
rw
SSC
state of SSCEN prior to the access, ie. writing C057
mode (SSCEN=’0’) will initialize the SSC (SSCEN was ‘0’) and then turn it on
(SSCEN=’1’).
• When writing to SSCCON, make sure that reserved locations receive zeros.
MS
14
rw
13
-
-
H
Function (Operating Mode, SSCEN = ‘1’)
SSC Bit Count Field
Shift counter is updated with every shifted bit. Do not write to!!!
SSC Transmit Error Flag
1 : Transfer starts with the slave’s transmit buffer not being updated
SSC Receive Error Flag
1 : Reception completed before the receive buffer was read
SSC Phase Error Flag
1 : Received data changes around sampling clock edge
SSC Baudrate Error Flag
1 : More than factor 2 or 0.5 between Slave’s actual and expected
SSC Busy Flag
Set while a transfer is in progress. Do not write to!!!
SSC Master Select Bit
0 : Slave Mode. Operate on shift clock received via SCLK.
1 : Master Mode. Generate shift clock and output it via SCLK.
SSC Enable Bit = ‘1’
Transmission and reception enabled. Access to status flags and M/S
control.
/ D9
SSC
BSY
12
rw
baudrate
H
)
SSC
BE
11
rw
SSC
PE
10
rw
SSC
RE
rw
9
SSC
TE
rw
8
SFR
308
High-Speed Synchronous Serial Interface
7
-
-
6
-
-
5
-
-
H
to SSCCON in programming
4
-
-
Reset Value: 0000
3
2
SSCBC
r
2001-04-19
1
C161U
0
H