SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 83

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

MDL (FE0E
Whenever this register is updated via software, the Multiply/Divide Register In Use
(MDRIU) flag in the Multiply/Divide Control register (MDC) is set to '1'. The MDRIU flag
is cleared, whenever the MDL register is read via software.
When a multiplication or division is interrupted before its completion and when a new
multiply or divide operation is to be performed within the interrupt service routine, register
MDL must be saved along with registers MDH and MDC to avoid erroneous results.
A detailed description of how to use the MDL register for programming multiply and
divide algorithms can be found in chapter “System Programming”.
Multiply/Divide Control Register MDC
This bit addressable 16-bit register is implicitly used by the CPU, when it performs a
multiplication or a division. It is used to store the required control information for the
corresponding multiply or divide operation. Register MDC is updated by hardware during
each single cycle of a multiply or divide instruction.
Data Sheet
Bit
mdl
15
14
H
/ 07
13
Function
Specifies the low order 16 bits of the 32-bit multiply and divide register
MD.
H
)
12
11
10
9
8
SFR
mdl
rw
83
7
6
5
4
Central Processor Unit
Reset Value: 0000
3
2
2001-04-19
1
C161U
0
H