SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 20

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Table 2
Pin No.
84-87, 90-92 P6.0-
97-98
34
35
37
Microprocessor Bus and Control Signals (cont’d)
Symbol
P6.3,
P6.5-
P6.7
P2.0-
P2.1
RD
WR/WRL O
ALE
Input (I)
Output (O)
O
I/O
O
...
O
I
O
O
I/O
I
I
O
O
Function
Port6 is an 7-bit bidirectional I/O port. It is bit-
wise programmable for input or output via
direction bits. For a pin configured as input, the
output driver is put into high-impedance state.
Port6 outputs can be configured as push/pull
or open-drain drivers.
P6.0
...
P6.3
P6.5
P6.6
P6.7
PORT2 is an 2-bit bidirectional I/O port. It is
bit-wise programmable for input or output via
direction bits. For a pin configured as input, the
output driver is put into high-impedance state.
Port2 outputs can be configured as push/pull
or open-drain drivers.
P2.0
P2.1
External Memory Read Strobe. RD is
activated for every external instruction or data
read access.
External Memory Write Strobe. In WR mode
this pin is activated for every external data
write access. In WRL mode this pin is
activated for low byte data write accesses on a
16-bit bus, and for every data write access on
an 8-bit bus. See WRCFG in register
SYSCON for mode selection.
Address Latch Enable Output. Can be used for
latching the address into external memory or
an address latch in the multiplexed bus
modes.
20
CS0
CS3
...
HOLD
HLDA
BREQ
EX0IN
EX1IN
Chip Select 0 Output
Chip Select 3 Output
...
Request Input
Hold Acknowledge Output
External Master Hold
Bus Request Output
Input
Input
Fast External Interrupt 0
Fast External Interrupt 1
Pin Descriptions
2001-04-19
C161U