SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 131

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

FEIxIC (See Table)
Note: Please refer to the general Interrupt Control Register description for an
Table 26
7.9
Traps interrupt the current execution similar to standard interrupts. However, trap
functions offer the possibility to bypass the interrupt system's prioritization process in
cases where immediate system reaction is required. Trap functions are not maskable
and always have priority over interrupt requests on any priority level.
C161U provides two different kinds of trapping mechanisms. Hardware traps are
triggered by events that occur during program execution (eg. illegal access or undefined
opcode), software traps are initiated via an instruction within the current execution flow.
Software Traps
TRAP instruction is used to cause a software call to an interrupt service routine. The trap
number that is specified in the operand field of the trap instruction determines which
vector location in the address range from 00’0000
to.
Executing a TRAP instruction causes a similar effect as if an interrupt at the same vector
had occurred. PSW, CSP (in segmentation mode), and IP are pushed on the internal
system stack and a jump is taken to the specified vector location. When segmentation is
enabled and a trap is executed, the CSP for the trap service routine is set to code
segment 0. No Interrupt Request flags are affected by the TRAP instruction. The
interrupt service routine called by a TRAP instruction must be terminated with a RETI
(return from interrupt) instruction to ensure correct operation.
Note: The CPU level in register PSW is not modified by the TRAP instruction, so the
Data Sheet
Register
FEI0IC
FEI1IC
15
-
explanation of the control fields.
service routine is executed on the same priority level from which it was invoked.
Therefore, the service routine entered by the TRAP instruction can be interrupted
14
-
Trap Functions
13
-
Fast External Interrupt Control Register Addresses
12
-
11
-
Address
FF88
FF8A
10
-
H
H
/ C4
/ C5
9
-
H
H
8
-
SFR
131
FEIx
IR
rw
7
FEIx
IE
rw
H
6
through 00’01FC
5
Interrupt and Trap Functions
External Interrupt
EX0IN
EX1IN
4
ILVL
rw
Reset Value: - - 00
3
H
will be branched
2
2001-04-19
1
GLVL
rw
C161U
0
HH