SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 331

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Suspend and Remote Resume Support
After entering the Suspend state, the UDC may start a RemoteWakeup sequence on the
USB, after the device has enabled the UDC clock supply. After the PLL VCO frequency
has been stabilized the DEV_Resume signal can be asserted which causes the UDC to
drive a resume (K-state) to the USB for 3 ms.
UDC provides a DEVICE_REMOTE_WAKEUP feature bit in the EndpointInfo block of
the UDC core. At power-on reset this bit is disabled and on a SetFeature command to
the device, this bit can be set by the host. The state of this bit is reflected on the
STATUS2 register.
15.4
USB Interface Controller architecture is shown in Figure 105 below. UDC provides the
48 MHz PLL for full-speed clock & data recovery, Serial Interface Engine (SIE) and the
USB Bridge Layer Block. The UDC is connected with its Application Bus Interface to the
Standard Module Interface (SMIF), which itself is hooked onto the BUS Peripheral
interface (BPI).
Figure 105
15.5
EPINFO Block is a configurable block which will be programmed at compile time . Since
the GetDescriptor command is forwarded to the Application, the EPINFO provides only
the registers used by the Application to download application specific configuration data.
The EPINFO block features in summary are:
Data Sheet
D+
D-
– DATA0/DATA1 Synchronization
– EndPtStalled Bit support
USB Interface Controller (USBD) Architecture
Endpoint Info Block
USB Interface Controller Architecture
UDC
PLL
SIE
EndPoint Info
331
UBL
Protocol
Layer
End
Point 0
Bus Interface
Application
USB Interface Controller
Control,
Arbiter &
MUX
XBUS
2001-04-19
C161U

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