SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 409

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

21.8
The instructions of the C161U are very efficient (most instructions execute in one
machine cycle) and even the multiplication and division are interruptable in order to
minimize the response latency to interrupt requests (internal and external). In many
microcontroller applications this is vital.
Some special occasions, however, require certain code sequences (eg. semaphore
handling) to be uninterruptable to function properly. This can be provided by inhibiting
interrupts during the respective code sequence by disabling and enabling them before
and after the sequence. The necessary overhead may be reduced by means of the
ATOMIC instruction which allows locking 1...4 instructions to an unseparable code
sequence, during which the interrupt system (standard interrupts and PEC requests)
and Class A Traps (NMI, stack overflow/underflow) are disabled. A Class B Trap
(illegal opcode, illegal bus access, etc.), however, will interrupt the atomic sequence,
since it indicates a severe hardware problem. The interrupt inhibit caused by an ATOMIC
instruction gets active immediately, ie. no other instruction will enter the pipeline except
the one that follows the ATOMIC instruction, and no interrupt request will be serviced in
between. All instructions requiring multiple cycles or hold states are regarded as one
instruction in this sense (eg. MUL is one instruction). Any instruction type can be used
within an unseparable code sequence.
ATOMIC
MOV
MOV
MUL
MOV
21.9
The standard mechanism to access data locations uses one of the four data page
pointers (DPPx), which selects a 16 KByte data page, and a 14-bit offset within this data
page. The four DPPs allow immediate access to up to 64 KByte of data. In applications
with big data arrays, especially in HLL applications using large memory models, this may
require frequent reloading of the DPPs, even for single accesses.
EXTP (extend page) instruction allows switching to an arbitrary data page for 1...4
instructions without having to change the current DPPs.
EXTP
MOV
MOV
Data Sheet
Unseparable Instruction Sequences
Overriding the DPP Addressing Mechanism
#3
R0, #1234H
R1, #5678H
R0, R1
R2, MDL
R15, #1
R0, [R14]
R1, [R13]
;The next 3 instr. are locked (No NOP requ.)
;Instr. 1 (no other instr. enters pipeline!)
;Instr. 2
;Instr. 3: MUL regarded as one instruction
;This instruction is out of the scope...
;...of the ATOMIC instruction sequence
;The override page number is stored in R15
;The (14-bit) page offset is stored in R14
;This instruction uses the std. DPP scheme!
409
System Programming
2001-04-19
C161U