SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 268

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Data transmission is double-buffered, so a new character may be written to the transmit
buffer register, before the transmission of the previous character is complete. This allows
the transmission of characters back-to-back without gaps.
Data reception is enabled by the Receiver Enable Bit CON_REN. After reception of a
character has been completed, the received data and, if provided by the selected
operating mode, the received parity bit can be read from the (read-only) Receive Buffer
register S0RBUF. Bits in the upper half of S0RBUF which are not valid in the selected
operating mode will be read as zeros.
Data reception is double-buffered, so that reception of a second character may already
begin before the previously received character has been read out of the receive buffer
register. In all modes, receive buffer overrun error detection can be selected through bit
CON_OEN. When enabled, the overrun error status flag CON_OE and the error interrupt
request line EIR will be acitvated when the receive buffer register has not been read by
the time reception of a second character is complete. The previously received character
in the receive buffer is overwritten.
The Loop-Back option (selected by bit CON_LB) allows the data currently being
transmitted to be received simultaneously in the receive buffer. This may be used to test
serial communication routines at an early stage without having to provide an external
network. In loop-back mode the alternate input/output function of port pins is not
required.
Note: Serial data transmission or reception is only possible when the Baudrate
12.1.5
Asynchronous mode supports full-duplex communication, where both transmitter and
receiver use the same data frame format and the same baudrate. Data is transmitted on
pin P3.10/TXD and received on pin P3.11/RXD. IrDA data transmission/reception is
supported up to 115.2 KBit/s. Figure 78 shows the block diagram of the ASC when
operating in asynchronous mode.
Generator Run Bit CON_R is set to ‘1’. Otherwise the serial interface is idle.
Do not program the mode control field COM_M to one of the reserved
combinations to avoid unpredictable behaviour of the serial interface
Asynchronous Operation
268
Asynchronous/Synchr. Serial Interface
2001-04-19
C161U