SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 53

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
Memory Organization
For PEC data transfers the external memory can be accessed independent of the
contents of the DPP registers via the PEC source and destination pointers.
The external memory is not provided for single bit storage and therefore it is not bit
addressable.
4.3
Crossing Memory Boundaries
The address space of the C161U is implicitly divided into equally sized blocks of different
granularity and into logical memory areas. Crossing the boundaries between these
blocks (code or data) or areas requires special attention to ensure that the controller
executes the desired operations.
Memory Areas are partitions of the address space that represent different kinds of
memory (if provided at all). These memory areas are the internal RAM/SFR area, the on-
chip X-Peripherals and the external memory.
Accessing subsequent data locations that belong to different memory areas is no
problem. However, when executing code, the different memory areas must be switched
explicitly via branch instructions. Sequential boundary crossing is not supported and
leads to erroneous results.
Note: Changing from the external memory area to the internal RAM/SFR area takes
place within segment 0.
Segments are contiguous blocks of 64 KByte each. They are referenced via the code
segment pointer CSP for code fetches and via an explicit segment number for data
accesses overriding the standard DPP scheme.
During code fetching segments are not changed automatically, but rather must be
switched explicitly. The instructions JMPS, CALLS and RETS will do this.
In larger sequential programs make sure that the highest used code location of a
segment contains an unconditional branch instruction to the respective following
segment, to prevent the prefetcher from trying to leave the current segment.
Data Pages are contiguous blocks of 16 KByte each. They are referenced via the data
page pointers DPP3...0 and via an explicit data page number for data accesses
overriding the standard DPP scheme. Each DPP register can select one of the possible
1024 data pages. The DPP register that is used for the current access is selected via the
two upper bits of the 16-bit data address. Subsequent 16-bit data addresses that cross
the 16 KByte data page boundaries therefore will use different data page pointers, while
the physical locations need not be subsequent within memory.
Data Sheet
53
2001-04-19