SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 447

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Figure 126
The CPU clock signal can be generated via different mechanisms. The mechanism used
to generate the CPU clock is selected during reset via the logic levels on pins P0.15-13
(P0H.7-5) and is described in detail in Chapter 3.3, page 35. The duration of TCLs and
their variation (and also the derived external timing) depends on the mechanism used to
generate f
C161U.
Note: The example for PLL operation shown in Figure 126 refers to a PLL factor of 4.
The PLL multiplies the input frequency by the factor F which is selected via the
combination of pins P0.15-13 (ie. f
PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done
smoothly, i.e. the CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock, the frequency of f
it is locked to f
duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator), the relative deviation for periods of more than one TCL is lower
than for a single TCL. This is especially important for bus cycles using wait-states and
for the operation of timers, serial interfaces, etc. For all slower operations and longer
periods (eg. pulse train generation or measurement, lower baudrates, etc.), the deviation
caused by the PLL jitter is negligible.
Data Sheet
Phase Locked Loop Operation
Prescaler Operation
f
f
XTAL
CPU
f
f
XTAL
CPU
CPU
. This influence must be regarded when calculating the timings for the
Generation mechanisms for the CPU Clock
XTAL
. The slight variation causes a jitter of f
CPU
= f
XTAL
447
* F). With every F’th transition of f
CPU
CPU
TCL
is constantly adjusted so
AC/DC Characteristics
which also affects the
TCL
TCL TCL
2001-04-19
C161U
XTAL
the