SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 322

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
A data packet consists of the following fields:
A handshake packet consists of the following fields:
Transaction
A transaction consists of a token packet, optional data packets and a handshake packet.
Transfer
A transfer consists of one or more transactions. Control transfers consists of a setup
transaction, optional data transactions and a handshake/status transaction.
15.3
Data transactions will be handled by the UDC core as a bus master via the application
bus interface. The 8-byte SETUP control data will be written into the USBD_SETUP
registers only, whereas subsequent data transactions will use endpoint 0 or another
endpoint specified by the SETUP packet.
In addition, the USBD FIFO/Control block provides eight (i.e. per endpoint) 8-byte
Transmit FIFOs for IN transfers and eight 8-byte Receive FIFOs for OUT transfers. The
Transmit FIFO is accessed by the USBD_TXWRn register and the Receive FIFO by the
USBD_RXRDn register from the CPU via XBUS. Each Receive and Transmit FIFO
provides a Packet-Complete indication register and interrupt USBD_TXDONEn/
USBD_RXDONEn, indicating a complete packet transfer from/to the CPU.
The basic FIFO structure is shown in Figure 102 below. Each endpoint FIFO pair
generates two transfer request interrupt to the EPEC. The USBD_TXREQn interrupt
indicates that the Transmit FIFO is able to accept words from the XBUS. The
USBD_RXREQn interrupt indicates an valid word in the Receive FIFO which can be
read.
The USBD control logic multiplexes the active FIFO input/output on the unidirectional
DEV_DATA or UDC_DATA bus.
– Address (7 bits)
– Endpoint (4 bits)
– CRC-5 (5 bits)
– SYNC byte (8 bits)
– Packet Identifier (8 bits)
– Data (n bytes)
– CRC-5 (5 bits)
– SYNC byte (8 bits)
– Packet Identifier (8 bits)
USB Endpoints
322
USB Interface Controller
2001-04-19
C161U