SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 357

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Figure 112
After sending the identification byte the ASC receiver is enabled and is ready to receive
the initial 32 bytes from the host. A half duplex connection is therefore sufficient to feed
the BSL.
Note: In order to properly enter BSL mode it is not only required to pull P0L.4 low,
Loading the Startup Code
After sending the identification byte the BSL enters a loop to receive 32 bytes via ASC.
These bytes are stored sequentially into locations 00’FA40
internal RAM. So up to 16 instructions may be placed into the RAM area. To execute the
loaded code the BSL then jumps to location 00’FA40
bootstrap loading sequence is now terminated, the C161U remains in BSL mode,
however. Most probably the initially loaded routine will load additional code or data, as
an average application is likely to require substantially more than 16 instructions. This
second receive loop may directly use the pre-initialized interface ASC to receive data
and store it to arbitrary user-defined locations.
This second level of loaded code may be the final application code. It may also be
another, more sophisticated, loader routine that adds a transmission protocol to enhance
the integrity of the loaded code or data. It may also contain a code sequence to change
the system configuration and enable the bus interface to store the received data into
external memory.
Data Sheet
but also pins P0L.2, P0L.3, P0L.5 must receive defined levels.
This is described in chapter "System Reset“.
P0L.4
Hardware Provisions to Activate the BSL
R
8 k
P0L.4
Circuit_1
357
P0L.4
H
, ie. the first loaded instruction. The
H
External Signal
through 00’FA5F
Bootstrap Loader
Normal Boot
BSL
R
8 k
P0L.4
Circuit_2
MCA02261
2001-04-19
H
C161U
of the