SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 34

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
accessed by the CPU at a time. The number of register banks is only restricted by the
available internal RAM space. For easy parameter passing, a register bank may overlap
others.
A system stack of up to 1024 words is provided as a storage for temporary data. The
system stack is also located within the on-chip RAM area, and it is accessed by the CPU
via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are
implicitly compared against the stack pointer value upon each stack access for the
detection of a stack overflow or underflow.
Hardware detection of the selected memory space is placed at the internal memory
decoders and allows the user to specify any address directly or indirectly and obtain the
desired data without using temporary registers or special instructions.
For Special Function Registers 1024 Bytes of the address space are reserved. The
standard Special Function Register area (SFR) uses 512 bytes, while the Extended
Special Function Register area (ESFR) uses the other 512 bytes. (E)SFRs are wordwide
registers which are used for controlling and monitoring functions of the different on-chip
units. Unused (E)SFR addresses are reserved for future members of the C161U family
with enhanced functionality.
External Bus Interface
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 2 MBytes of external RAM and/or ROM can be connected to the
microcontroller via its external bus interface. The integrated External Bus Controller
(EBC) allows to access external memory and/or peripheral resources in a very flexible
way. For up to five address areas the bus mode (multiplexed / demultiplexed), the data
bus width (8-bit / 16-bit) and even the length of a bus cycle (waitstates, signal delays)
can be selected independently. This allows to access a variety of memory and peripheral
components directly and with maximum efficiency. If the device does not run in Single
Chip Mode, where no external memory is required, the EBC can control external
accesses in one of the following four different external access modes:
The demultiplexed bus modes use PORT1 for addresses and PORT0 for data input/
output. The multiplexed bus modes use PORT0 for both addresses and data input/
output. All modes use Port 4 for the upper address lines (A16...) if selected.
Important timing characteristics of the external bus interface (waitstates, ALE length and
Read/Write Delay) have been made programmable to allow the user the adaption of a
wide range of different types of memories and/or peripherals. Access to very slow
memories or peripherals is supported via a particular 'Ready' function.
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
34
Architectural Overview
2001-04-19
C161U