SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 277

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
Asynchronous/Synchr. Serial Interface
12.1.6.1 Synchronous Transmission
Synchronous transmission begins within 4 state times after data has been loaded into
S0TBUF provided that CON_R is set and CON_REN=’0’ (half-duplex, no reception).
Exception : in loopback mode (bit CON_LB set), CON_REN must be set for reception of
the transmitted byte. Data transmission is double buffered. When the transmitter is idle,
the transmit data loaded into S0TBUF is immediately moved to the transmit shift register
thus freeing S0TBUF for the next data to be sent. This is indicated by the transmit buffer
interrupt request line TBIR being activated. S0TBUF may now be loaded with the next
data, while transmission of the previous one is still going on. The data bits are
transmitted synchronous with the shift clock. After the bit time for the 8th data bit, both
TXD and RXD will go high, the transmit interrupt request line TIR is activated, and serial
data transmission stops.
Pin P3.10/TXD must be configured for alternate data output in order to provide the shift
clock. Pin P3.11/RXD must also be configured for output during transmission.
12.1.6.2 Synchronous Reception
Synchronous reception is initiated by setting bit CON_REN=’1’. If bit CON_R=1, the data
applied at RXD is clocked into the receive shift register synchronous to the clock which
is output at pin TXD. After the 8th bit has been shifted in, the content of the receive shift
register is transferred to the receive data buffer RBUF, the receive interrupt request line
RIR is activated, the receiver enable bit CON_REN is reset, and serial data reception
stops.
Pin P3.10/TXD must be configured for alternate data output in order to provide the shift
clock. Pin P3.11/RXD must be configured as alternate data input.
Synchronous reception is stopped by clearing bit CON_REN. A currently received byte
is completed including the generation of the receive interrupt request and an error
interrupt request, if appropriate. Writing to the transmit buffer register while a reception
is in progress has no effect on reception and will not start a transmission.
If a previously received byte has not been read out of the receive buffer register at the
time the reception of the next byte is complete, both the error interrupt request line EIR
and the overrun error status flag CON_OE will be activated/set, provided the overrun
check has been enabled by bit CON_OEN.
Data Sheet
277
2001-04-19