SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 94

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
6
EPEC provides fast and easy means to transfer single data between any memory
location within the address space by using the XBUS. The advantages are reduced
XBUS protocol handling and capability of addressing all system resources including
internal RAM and SFR.
6.1
EPEC provides a DMA controller for the USB device core to provide fast and flexible data
tranfer capability. EPEC is implemented as a 16 channel controller with a 24-bit source
pointer, a 24-bit destination pointer and a 10-bit Transmit Byte Length Counter with auto-
increment support of two bytes (one word) per channel with Terminal Count (TC)
indication (Interrupt pulse valid for one clock cycle). After TC is reached, the counter
stops itself.
EPEC is connected to the XBUS and to a proprietary 24-bit bus connected directly to the
C166 CBC. EPEC has the highest priority among other interrupts and PECs and does
not participate in the interrupt priorization round. In case of an DPEC/EPEC collision, the
DPEC will get priority and one instruction cycle later the EPEC is processed. EPEC
provides DMA like functionality by injecting a memory transfer instruction (mov [dest],
[src]) into the decode stage of the pipeline and thus only needs one additional instruction
cycle. Even in IDLE mode, the EPEC will be processed waking up the CPU for one
instruction cycle and immediately going back to IDLE state.
6.2
EPEC control block is located in the CBC core with its main purpose to synchronize the
external EPEC request to the internal T1-T4 states of the CPU and the priorization
between DPEC and EPEC. It also drives the externally provided 24-bit source and
destination pointer values on the internal memory address bus, thus controlling the
whole timing with respect to the CPU.
DMA - External PEC (EPEC)
EPEC Functionality
EPEC Implementation
94
DMA - External PEC (EPEC)
2001-04-19
C161U