SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 114

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Note: All requests on levels 13...1 cannot initiate PEC transfers. They are always
Interrupt Control Functions in the PSW
The Processor Status Word (PSW) is functionally divided into 2 parts: the lower byte of
the PSW basically represents the arithmetic status of the CPU, the upper byte of the
PSW controls the interrupt system of the C161U and the arbitration mechanism for the
external bus interface.
Note: Pipeline effects have to be considered when enabling/disabling interrupt requests
PSW (FF10
CPU Priority ILVL defines the current level for the operation of the CPU. This bit field
reflects the priority level of the routine that is currently executed. Upon entry into an
interrupt service routine this bit field is updated with the priority level of the request that
is being serviced. The PSW is saved on the system stack before. The CPU level
Bit
N, C, V, Z,
E, MULIP,
USR0
HLDEN
ILVL
IEN
15
serviced by an interrupt service routine. No PECC register is associated and no
COUNT field is checked.
via modifications of register PSW (see chapter “The Central Processing Unit”).
14
ILVL
rw
H
/ 88
13
Function
CPU status flags (Described in section “The Central Processing Unit”)
Define the current status of the CPU (ALU, multiplication unit).
HOLD Enable (Enables External Bus Arbitration)
0:
1:
CPU Priority Level
Defines the current priority level for the CPU
F
0
Interrupt Enable Control Bit (globally enables/disables interrupt
requests)
‘0’:
‘1’:
H
H
H
)
:
:
12
IEN
Bus arbitration disabled, P6.7...P6.5 may be used for general
purpose I/O
Bus arbitration enabled, P6.7...P6.5 serve as BREQ, HLDA,
HOLD, resp.
Highest priority level
Lowest priority level
Interrupt requests are disabled
Interrupt requests are enabled
11
rw
HLD
EN
10
rw
9
-
-
8
-
-
SFR
114
7
-
-
USR0
rw
6
MUL
IP
rw
5
Interrupt and Trap Functions
rw
E
4
rw
Reset Value: 0000
3
Z
rw
V
2
rw
2001-04-19
C
1
C161U
rw
N
0
H