SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 368

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Figure 116
Note: The configuration on pins P0H.7:P0H.5 (CLKCFG) and P0L5:P0L.2 (SMOD) is
The configuration via P0H is latched in register RP0H for subsequent evaluation by
software. Register RP0H is described in chapter “The External Bus Interface”.
Note: The reset configuration needs to be held on port P0 throughout the start-up phase
The following describes the different selections that are offered for reset configuration.
The default modes refer to pins at high level, ie. without external pulldown devices
connected. Table 91 shows a summary of all modes, supported by the C161U.
Configuration latched in on hardware reset
Configuration latched in on software and/or WDT reset
H.7 H.6 H.5 H.4
H.7 H.6 H.5 H.4
Generator
CLKCFG
Clock
latched in on a hardware triggered reset only and will not be evaluated by the
C161U on a software and/or WDT reset.
until the C161U takes over control of the external XBUS. This is first indicated by
driving the XBUS output lines ALE, RD, WR/WRL, CS, P4, P1H and P1L. Since it
might prove infeasible to detect the change from tristate to a strongly driven value,
the first rising edge of ALE can be used for indication of the end of the reset
configuration hold time. The first rising edge of ALE occurs 4 CPU cycles after
taking control of the external bus.
PORT0 Configuration during Reset
H.4
SALSEL
Port 4
Logic
H.3 H.2 H.1 H.0 L.7 L.6
H.3 H.2 H.1 H.0 L.7 L.6
H.3 H.2 H.1 H.0 L.7 L.6
SYSCON
CSSEL
Port 6
Logic
WRC
368
BUSTYP
BUSCON0
L.5 L.4 L.3 L.2 L.1 L.0
L.5 L.4 L.3 L.2 L.1 L.0
Internal Control Logic
SMOD
System Reset
ADP
L.1 L.0
2001-04-19
C161U
P0L.0
must
always
be ’1’
’1’