SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 343

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

USBD_TXWRn (n=7..0)
Table 84
The USB TXWR0 register provides 16-bit write access to the Endpoint#n Transmit FIFO.
USBD_TXEODn (n=7..0)
Table 85
The USB TXEODn register provides 16-bit read/write access. Indicates that the EPEC/
SW has sent the last valid data byte to the Endpoint’s#n Transmit FIFO. Writing ’1’ to the
register makes the next request for a data packet from Host answered by C161U with an
empty data packet.
As long as a ’1’ is stored in the register, the packet has not been transfered to the host.
If transferred, the bit is cleared.
Note: If bit TXEOD is written at the time an IN request from the host - due to missing
Data Sheet
Bit No. Bit
(15:0)
Bit No. Bit
(15:1)
0
transmit data - is answered by a NACK packet, bit TXEOD is cleared and the
tx_done interrupt is asserted although the NACK packet has been sent instead of
the empty packet.
Therefore, prior to setting the TXEOD bit, Software must reset the endpoint’s
acknowledge-bit TX_XFR_ACKn in register USBD_STATUS_REG1. In reaction
to endpoint’s tx_done interrupt, Software always should check the value of
TX_XFR_ACKn to verify that the previous data transfer succeeded. If
TX_XFR_ACKn indicates an unsuccessful data transmission, Software must
repeat the transfer.
TXWRn
TXEOD
USBD_TXWRn Transmit Data FIFO EP#n Register
USBD_TXEODn Transmit End-of-packet Register
Reset Value: 0000
Reset Value: 0000
Function
16-bit word for Transmit FIFO endpoint#n (n=7..0)
Function
reserved
’1’: Indicates last byte of packet transferred to
’0’: EPEC/SW is idle/busy
Transmit FIFO endpoint#n (n=7..0)
343
H
H
USB Interface Controller
2001-04-19
C161U