SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 323

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
C161U
USB Interface Controller
A 10-bit receive byte counter counts the length of the currently receiving packet. This
length information together with an endpoint/packet status will be provided in the length
register after the packet is received completely.
For SW syncronization purposes, an 1 ms Start-of-Frame (SOF) interrupt will be
generated periodically by the USB host. The frame number will be captured for each
received frame.
No data available for an Interrupt, Bulk or Control endpoint for the dedicated Transmit
FIFO will result in a NACK, generated by the UDC. No Receive FIFO space available will
result also in a NACK. Additionally, for receive function the RX byte count register has to
be read. Otherwise the next packet will be NACKed.
In transmit direction, the software has to read the STATUS bit from the
USBD_STATUS_REG1 register after transferring the packet in order to determine
whether the transfer was ACKed or NACKed by the host.
The SW can STALL or resume the device from suspend mode by using the command
register USBD_CMD_REG.
Data Sheet
323
2001-04-19

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