SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 48

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Note: The upper 256 Bytes of SFR area, ESFR area and internal RAM are bit-
Code accesses are always made on even byte addresses. The highest possible code
storage location in the internal RAM is either 00’FDFE
00’FDFC
instruction (unconditional), because sequential boundary crossing from internal RAM to
the SFR area is not supported and causes erroneous results.
Any word and byte data in the internal RAM can be accessed via indirect or long 16-bit
addressing modes, if the selected DPP register points to data page 3. Any word data
access is made on an even byte address. The highest possible word data storage
location in the internal RAM is 00’FDFE
be accessed independent of the contents of the DPP registers via the PEC source and
destination pointers.
The upper 256 Byte of the internal RAM (00’FD00
the current bank are provided for single bit storage, and thus they are bit addressable.
System Stack
The system stack may be defined within the internal RAM. The size of the system stack
is controlled by bitfield STKSZ in register SYSCON (see table below).
For all system stack operations the on-chip RAM is accessed via the Stack Pointer (SP)
register. The stack grows downward from higher towards lower RAM address locations.
Only word accesses are supported to the system stack. A stack overflow (STKOV) and
a stack underflow (STKUN) register are provided to control the lower and upper limits of
the selected stack area. These two stack boundary registers can be used not only for
protection against data destruction, but also allow to implement a circular stack with
hardware supported system stack flushing and filling (except for option ’111’).
<STKSZ>
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
addressable (see shaded blocks in Figure 10).
B
B
B
B
B
B
B
B
H
for double word instructions. The respective location must contain a branch
Stack Size
(Words)
256
128
64
32
512
---
---
1024
Internal RAM Addresses (Words)
00’FBFE
00’FBFE
00’FBFE
00’FBFE
00’FBFE
Reserved. Do not use this combination.
Reserved. Do not use this combination.
00’FDFE
H
. For PEC data transfers, the internal RAM can
48
H
H
H
H
H
H
...00’FA00
...00’FB00
...00’FB80
...00’FBC0
...00’F800
...00’F600
H
through 00’FDFF
H
H
H
H
H
H
H
(Note: No circular stack)
for single word instructions or
(Default after Reset)
Memory Organization
H
) and the GPRs of
2001-04-19
C161U