SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 67

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Note: Register SYSCON cannot be changed after execution of the EINIT instruction.
System Clock Output Enable (CLKEN)
The system clock output function is enabled by setting bit CLKEN in register SYSCON
to '1'. If enabled, port pin P3.15 takes on its alternate function as CLKOUT output pin.
The clock output is a 50 % duty cycle clock whose frequency equals the CPU operating
frequency (f
Note: The output driver of port pin P3.15 is switched on automatically, when the
Segmentation Disable/Enable Control (SGTDIS)
Bit SGTDIS allows to select either the segmented or non-segmented memory mode.
In non-segmented memory mode (SGTDIS='1') it is assumed that the code address
space is restricted to 64 KBytes (segment 0) and thus 16 bits are sufficient to represent
all code addresses. For implicit stack operations (CALL or RET) the CSP register is
totally ignored and only the IP is saved to and restored from the stack.
In segmented memory mode (SGTDIS='0') it is assumed that the whole address space
is available for instructions. For implicit stack operations (CALL or RET) the CSP register
Data Sheet
Bit
ROMEN
SGTDIS
ROMS1
STKSZ
CLKOUT function is enabled. The port direction bit is disregarded.
After reset, the clock output function is disabled (CLKEN = ‘0’).
OUT
System Stack Size
Function
Internal Boot-ROM Enable
’0’:
’1’:
Segmentation Disable/Enable Control
’0’:
’1’:
Reserved
The ROMS1, known from other C16x Infineon derivatives, is not
supported in the C161U. This bit must be set to ’0’ signal.
Selects the size of the system stack (in the internal RAM) from 32 to 1024
words
= f
CPU
).
Internal Boot-ROM is disabled. Access of the lower 32k address
space will be linked to external memory. During normal
operation, bit ROMEN must always be set to ’0’ signal
Internal Boot-ROM is enabled. This bit is only set in BSL mode.
During BSL mode, if the lowest 32k of external memory needs
to be programmed, bit ROMEN must be set to ’0’ signal. After
BSL mode, make sure that bit ROMEN is cleared.
Segmentation enabled
(CSP and IP are saved/restored during interrupt entry/exit)
Segmentation disabled (Only IP is saved/restored)
67
Central Processor Unit
2001-04-19
C161U