SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 362

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
The input RSTIN provides an internal pullup device equalling a resistor of 100 K
660 K
connecting an external capacitor is sufficient for an automatic power-on reset, see b) in
Figure 114. RSTIN may also be connected to the output of other logic gates, see a)
same figure.
Note: A power-on reset requires an active time of two reset sequences (1036 CPU clock
Software Reset
The reset sequence can be triggered at any time via the protected instruction SRST
(Software Reset). This instruction can be executed deliberately within a program, eg. to
leave bootstrap loader mode, or upon a hardware trap that reveals a system failure.
C161U’s latched in reset configuration on software reset is shown in Figure 116,
page 368.
Watchdog Timer Reset
When the watchdog timer is not disabled during the initialization or serviced regularly
during program execution it will overflow and trigger the reset sequence. Other than
hardware and software reset the watchdog reset completes a running external bus cycle
if this bus cycle either does not use READY at all, or if READY is sampled active (low)
after the programmed waitstates. When READY is sampled inactive (high) after the
programmed waitstates the running external bus cycle is aborted. Then the internal reset
sequence is started.
Note: For latched in watchdog reset configuration, refer to Figure 116, page 368.
C161U’s Pins after Reset
After the reset sequence the different groups of pins of the C161U are activated in
different ways depending on their function. Bus and control signals are activated
immediately after the reset sequence according to the configuration latched from
PORT0, so either external accesses can take place or the external control signals are
inactive. The general purpose I/O pins remain in input mode (high impedance) until
reprogrammed via software (see figure below). The RSTOUT pin remains active (low)
until the end of the initialization routine (see description).
cycles) after a stable clock signal is available (about 10...50 ms to allow the on-
chip oscillator to stabilize).
The watchdog reset cannot occur while the C161U is in bootstrap loader mode!
(the minimum reset time must be determined by the lowest value). Simply
362
System Reset
2001-04-19
C161U
to