SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 90

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
The PEC transfer counter allows to service a specified number of requests by the
respective PEC channel, and then (when COUNT reaches 00
service routine, which is associated with the priority level. After each PEC transfer the
COUNT field is decremented and the request flag is cleared to indicate that the request
has been serviced.
Continuous transfers are selected by the value FF
COUNT is not modified and the respective PEC channel services any request until it is
disabled again.
When COUNT is decremented from 01
cleared, which generates another request from the same source. When COUNT already
contains the value 00
interrupt service routine is activated instead. This allows to choose, if a level 15 or 14
request is to be serviced by the PEC or by the interrupt service routine.
Note: PEC transfers are only executed, if their priority level is higher than the CPU level,
Channel Link control bit CL controls the channel link mode. In this mode PEC
channels work by pair (channels 0 and 1, 2 and 3, 4 and 5, 6 and 7). The channel link
mode is enabled for one pair when the CL bit is set in any of the 2 PECCx registers. In
this case, the 2 channels handle PEC requests alternative to each other. The whole data
transfer is divided into several block transfers where each block is controlled by a PEC
channel. When a block transfer is completed, a channel link interrupt is generated and
the request processing is switched to the other PEC channel of the pair. This mechanism
allows to set up shadow and multiple buffers for PEC transfers by changing pointers and
count values of one channel when the other channel is active.
The very first transfer is always initiated with the even channel (called channel A, that is
channel 0, 2, 4 or 6). When the associated count field reaches 0 (COUNT or COUNT2
depending on the selected mode), the request service is transfered to the odd channel
(channel B, that is channel 1, 3, 5 or 7). If the CL bit of the "linked" channel is set and the
count field is different from 0, the next PEC requests will be serviced by this channel.
The channel link interrupts share one common interrupt node (Trap number 4C
location 00’0130
Control (CLISNC) register. It raises an interrupt request in case of one or more channel
link request flag and the respective enable control bit is set in CLISNC register. These
flags signal a PEC condition of the PEC linked channels which requires an action from
the CPU. The following conditions are possible:
1. In single transfer mode, a COUNT value change from 01
channel and the CL flag is set in the respective PEC control register,
ie. only PEC channels 7...4 are processed, while the CPU executes on level 14.
All interrupt request sources that are enabled and programmed for PEC service
should use different channels. Otherwise only one transfer will be performed for
all simultaneous requests. When COUNT is decremented to 00
to be interrupted, an incorrect interrupt vector will be generated.
H
). This node is controlled by the Channel Link Interrupt Sub-Node
H
, the respective PEC channel remains idle and the associated
H
to 00
90
H
after a transfer, the request flag is not
H
in bit field COUNT. In this case
H
Central Processor Unit
H
to 00
) activate the interrupt
H
H
, and the CPU is
in a linked PEC
2001-04-19
H
C161U
- vector