SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 330

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
= 7 * (4 * TCL + 2 * TCL) + 2 * (2* TCL) + (4 * TCL + 2 * TCL)
= 52 * TCL = 1.092 s
with f
= 7 * ext. bus accesses with 1 waitstate + 2 * states + 1 * ext. access for src/dest. pointer
= 7 * (4 * TCL + 2 * TCL) + 2 * (2 * TCL) + (4 * TCL + 2 * TCL)
= 52 * TCL = 722.3 ns
Best case: When instructions N and N-1 are executed out of external memory, but all
operands for instructions N-3 through N-1 are in internal memory, then the EPEC
response time is the time to execute 1 word bus access plus 2 state times (2*TCL).
with f
= 1* ext. bus accesses with 1 waitstate + 2 * states
= 1* (4 * TCL + 2 * TCL) + 2 * (2* TCL)
= 10 * TCL = 210 ns
with f
= 1* ext. bus accesses with 1 waitstate + 2 * states
= 1* (4 * TCL + 2 * TCL) + 2 * (2 * TCL)
= 10* TCL = 138.9 ns
Once a request for EPEC has been acknowledged by the CPU, the execution of the next
instruction is delayed by 2 state times plus the additional time it might take to fetch the
source operand from internal RAM or external memory and to write the destination over
the external bus in an external program environment.
A bus access in this context also includes delays by an external READY signal or by bus
arbitration (HOLD mode).
Suspend and Host Resume Support
UDC has built in counters, to count 6 ms idle time on the USB, which detects a Suspend
and 3 ms counter to send the RemoteWakeup sequence to the host. The
UDC_Suspend_Set interrupt will gate the indicate the Suspend mode to the application.
In response to this signal Software is supposed to turn off the clock of all the modules
which are not used at that moment in order to support a low power consumption. The
USB interface module clock can be switched off by SW using the USBCLC register.
The RemoteWakeup detection will deassert the UDC_Suspend for at least 20 ms, which
will generate a second interrupt UDC_Suspend_Off. The application will restart the UDC
and XBus clock supply as soon as possible.
Note: The normal suspend_off interrupt can not be generated if the USB clock is
CPU
CPU
CPU
switched off. In this case, the fast external interrupt
instead.
@36 MHz (TCL=13.89 ns) and 1 external waitstate:
@24 MHz (TCL=21ns) and 1 external waitstate:
@36 MHz (TCL=13.89 ns) and 1 external waitstate:
330
EX5INT (
USB Interface Controller
firq(5)) must be used
2001-04-19
C161U

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