SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 51

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Whenever a PEC data transfer is performed, the pair of source and destination pointers,
which is selected by the specified PEC channel number, is accessed independent of the
current DPP register contents and also the locations referred to by these pointers are
accessed independent of the current DPP register contents. If a PEC channel is not
used, the corresponding pointer locations area available and can be used for word or
byte data storage.
For more details about the use of the source and destination pointers for PEC data
transfers see section “Interrupt and Trap Functions”.
Special Function Registers
The functions of the CPU, the bus interface, the I/O ports and the on-chip peripherals of
the C161U are controlled via a number of so-called Special Function Registers (SFRs).
These SFRs are arranged within two areas of 512 Byte size each. The first register block,
the
(00’FFFF
located in the 512 Bytes below the internal RAM (00’F1FF
Special function registers can be addressed via indirect and long 16-bit addressing
modes. Using an 8-bit offset together with an implicit base address allows to address
word SFRs and their respective low bytes. However, this does not work for the
respective high bytes!
Note: Writing to any byte of an SFR causes the non-addressed complementary byte to
The upper half of each register block is bit-addressable, so the respective control/status
bits can directly be modified or checked using bit addressing.
When accessing registers in the ESFR area using 8-bit addresses or direct bit
addressing, an Extend Register (EXTR) instruction is required before, to switch the short
addressing mechanism from the standard SFR area to the Extended SFR area. This is
not required for 16-bit and indirect addresses. The GPRs R15...R0 are duplicated, ie.
they are accessible within both register blocks via short 2-, 4- or 8-bit addresses without
switching.
ESFR_SWITCH_EXAMPLE
EXTR
MOV
BFLDL
BSET
MOV
Data Sheet
SFR
be cleared!
H
...00’FE00
#4
ODP2, #data16
DP6, #mask, #data8
DP1H.7
T8REL, R1
area,
is
H
), the second register block, the Extended SFR (ESFR) area, is
located
in
;Bit addressing for single bits
;T8REL uses 16-bit mem address,
;Switch to ESFR area for next 4 instr.
;ODP2 uses 8-bit reg addressing
;Bit addressing for bit fields
;R1 is duplicated into the ESFR space
;(EXTR is not required for this access)
the
51
512
Bytes
above
H
...00’F000
Memory Organization
the
H
).
internal
2001-04-19
C161U
RAM