SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 182

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
Note: Never change the configuration for an address area that currently supplies the
The usage of the BUSCON/ADDRSEL registers is controlled via the issued addresses.
When an access (code fetch or data) is initiated, the respective generated physical
address defines, if the access is made internally, uses one of the address windows
defined by ADDRSEL4...1, or uses the default configuration in BUSCON0. After
initializing the active registers, they are selected and evaluated automatically by
interpreting the physical address. No additional switching or selecting is necessary
during run time, except when more than the four address windows plus the default is to
be used.
Switching from demultiplexed to multiplexed bus mode represents a special case.
The bus cycle is started by activating ALE and driving the address to Port 4 and PORT1
as usual, if another BUSCON register selects a demultiplexed bus. However, in the
multiplexed bus modes the address is also required on PORT0. In this special case the
address on PORT0 is delayed by one CPU clock cycle, which delays the complete
(multiplexed) bus cycle and extends the corresponding ALE signal (see figure below).
This extra time is required to allow the previously selected device (via demultiplexed bus)
to release the data bus, which would be available in a demultiplexed bus cycle.
instruction stream. Due to the internal pipelining it is very difficult to determine the
first instruction fetch that will use the new configuration. Only change the
configuration for address areas that are not currently accessed. This applies to
BUSCON registers as well as to ADDRSEL registers.
182
External Bus Interface
2001-04-19
C161U

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