SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 353

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Note: An internal power-on detection circuitry, also known from other C16x devices, is
Table 90
Type of Reset
Hardware reset via pin RSTIN
Software reset via command SRST
Watchdog Timer reset
Note: The WDTCON register bits [7, 6, 5] 4, 3, 2 and 1 are cleared by the EINIT
After any software reset, external hardware reset, or watchdog timer reset, the watchdog
timer is enabled and starts counting up from 0000
frequency may be switched to f
be disabled via the instruction DISWDT (Disable Watchdog Timer). Instruction DISWDT
is a protected 32-bit instruction which will ONLY be executed during the time between a
reset and execution of either the EINIT (End of Initialization) or the SRVWDT (Service
Watchdog Timer) instruction. Either one of these instructions disables the execution of
DISWDT.
When the watchdog timer is not disabled via instruction DISWDT, it will continue
counting up, even during Idle Mode. If it is not serviced via the instruction SRVWDT by
the time the count reaches FFFF
reset. This reset will pull the external reset indication pin RSTOUT low. It differs from a
software or external hardware reset in that bit WDTR (Watchdog Timer Reset Indication
Flag) of register WDTCON will be set. A hardware reset or the SRVWDT instruction will
clear this bit. Bit WDTR can be examined by software in order to determine the cause of
the reset.
A watchdog reset will also complete a running external bus cycle before starting the
internal reset sequence if this bus cycle does not use READY or samples READY active
(low) after the programmed waitstates. Otherwise the external bus cycle will be aborted.
Note: After a hardware reset that activates the Bootstrap Loader the watchdog timer will
To prevent the watchdog timer from overflowing, it must be serviced periodically by the
user software. The watchdog timer is serviced with the instruction SRVWDT, which is a
protected 32-bit instruction. Servicing the watchdog timer clears the low byte and reloads
the high byte of the watchdog timer register WDT with the preset value from bitfield
WDTREL which is the high byte of register WDTCON. Servicing the watchdog timer will
Data Sheet
not implemented. Therefore, bit WDTCON.5 (in other devices called PONR -
power-on reset) is reserved.
command.
be disabled.
WDTCON Register: Reset Source Identification
CPU
H
the watchdog timer will overflow and cause an internal
/128 by setting bit WDTIN. The watchdog timer can
WDTCON
Reset Value
001C
0004
0006
353
H
H
H
H
with the frequency f
WDTCON Flags being set
LHWR, SHWR, SWR
SWR
SWR, WDTR
Watchdog Timer (WDT)
CPU
/2. The input
2001-04-19
C161U