SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 235

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Figure 72
11.1.2.2 Auxiliary Timer T5
The auxiliary timer T5 can be configured for timer mode with the same options for the
timer frequencies and the count signal as the core timer T6. In addition, the auxiliary
timer can be concatenated with the core timer.
The individual configuration for timer T5 is determined by its bitaddressable control
register T5CON. Note that functions which are present in both timers of timer block 2 are
controlled in the same bit positions and in the same manner in each of the specific control
registers.
Run control for auxiliary timer T5 can be handled by the associated Run Control Bit T5R
in register T5CON. Alternatively, a remote control option (T5RC = ’1’) may be enabled
to start and stop T5 via the run bit T6R of core timer T6.
Note: The auxiliary timer has no overflow/underflow toggle latch. Therefore, an output
Count Direction Control for Auxiliary Timer
The count direction of the auxiliary timer can be controlled in the same way as for the
core timer T6. The description and the table apply accordingly.
Timer T5 in Counter Mode
Counter mode for the auxiliary timer T5 is selected by setting bit field T5M in register
T5CON to ‘001
output signal T6OFL only.
Data Sheet
line for Overflow/Underflow Monitoring is not provided.
f
hw_clk
Block Diagram of Core Timer T6 in Timer Mode
B
TxUD
’. In counter mode, timer T5 can be clocked by a transition of timer T6’s
2
Txl
n
: 1
TxUDE
TxR
Core Timer Tx
235
Up/
Down
General Purpose Timer Unit
x = 6
Interrupt
Request
TxOTL
MCB02028
2001-04-19
C161U