SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 103

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

EPEC_INTMSK_REG
Table 20
The EPEC interrupt mask register masks out the end of an TX-packet transfer interrupt
for an USB endpoint.
6.4
The EPEC (external peripheral event controller, external in the sense that it is external
to the CPU block) controls the transfer of data between the USB block and the external
or internal RAM.
Note:
The sequence of operations is as follows:
1. The USB block will generate FIFO request signals as soon as the system reset was
2. Now the USB has to be configured. The EPEC channel that serves USB
3. Now the EPEC channel for endpoint_0_IN can be activated by setting the enable bit
4. The transfer of configuration data to the USB FIFO for endpoint_0_IN starts because
5. After the EPEC byte counter has reached the number of bytes that have to be
6. The indication of the transmit end of data condition triggers the generation of the
Data Sheet
Bit No. Name
15:8
7:0
deasserted. It thus signals to the EPEC that the USB FIFOs are ready to receive data.
endpoint_0_IN is setup with source and destination pointer, the EPEC control register
is programmed with the number of bytes that need to be transfered and the bit for
external/ internal source has to be set according to the application.
in EPEC control register for endpoint_0_IN.
the USB FIFO has signaled that there is space available and the EPEC channel has
been enabled.
transfered, the EPEC channel disables itself and indicates the transmit end of data
condition in the EPEC interrupt register.
EPEC interrupt pulse to the CPU on the irq(40) line.
If the EPEC is not enabled, then no transfer is possible.
RxTxSTARTMSK
TXDONE_INTMSKx
(x=7..0)
EPEC Transfer Example
EPEC_INTMSK_REG Interrupt Register
Reset Value: 0000
Function
Rx / Tx Start Mask
’1’: masked
’0’: not masked
Mask interrupt TX packet transfer completed by
EPEC
’1’: masked
’0’: not masked
103
H
DMA - External PEC (EPEC)
2001-04-19
C161U