SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 312

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
from which it expects data either by separate select lines, or by sending a special
command to this slave.
After performing all necessary initializations of the SSC, the serial interfaces can be
enabled. For a master device, the alternate clock line will now go to its programmed
polarity. The alternate data line will go to either '0' or '1', until the first transfer will start.
After a transfer the alternate data line will always remain at the logic level of the last
transmitted data bit.
When the serial interfaces are enabled, the master device can initiate the first data
transfer by writing the transmit data into register SSCTB. This value is copied into the
shift register (which is assumed to be empty at this time), and the selected first bit of the
transmit data will be placed onto the MTSR line on the next clock from the baudrate
generator (transmission only starts, if SSCEN=’1’). Depending on the selected clock
phase, also a clock pulse will be generated on the SCLK line. With the opposite clock
edge the master at the same time latches and shifts in the data detected at its input line
MRST. This “exchanges” the transmit data with the receive data. Since the clock line is
connected to all slaves, their shift registers will be shifted synchronously with the
master's shift register, shifting out the data contained in the registers, and shifting in the
data detected at the input line. After the preprogrammed number of clock pulses (via the
data width selection) the data transmitted by the master is contained in all slaves’ shift
registers, while the master's shift register holds the data of the selected slave. In the
master and all slaves the content of the shift register is copied into the receive buffer
SSCRB and the receive interrupt flag SSCRIR is set.
A slave device will immediately output the selected first bit (MSB or LSB of the transfer
data) at pin MRST, when the content of the transmit buffer is copied into the slave's shift
register. It will not wait for the next clock from the baudrate generator, as the master
does. The reason for this is that, depending on the selected clock phase, the first clock
edge generated by the master may be already used to clock in the first data bit. So the
slave's first data bit must already be valid at this time.
Note: On the SSC always a transmission and a reception takes place at the same time,
Initialization of the SCLK pin on the master requires some attention in order to avoid
undesired clock transitions, which may disturb the other receivers. The state of the
internal alternate output lines is '1' as long as the SSC is disabled. This alternate output
signal is ANDed with the respective port line output latch. Enabling the SSC with an idle-
low clock (SSCPO=’0’) will drive the alternate data output and (via the AND) the port pin
SCLK immediately low. To avoid this, use the following sequence:
• select the clock idle level (SSCPO=’x’)
• load the port output latch with the desired clock idle level (P3.13=’x’)
• switch the pin to output (DP3.13=’1’)
• enable the SSC (SSCEN=’1’)
regardless whether valid data has been transmitted or received. This is different
eg. from asynchronous reception on ASC.
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High-Speed Synchronous Serial Interface
2001-04-19
C161U