SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 62

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
5.2
C161U provides several mechanisms to manipulate bits. These mechanisms either
manipulate software flags within the internal RAM, control on-chip peripherals via control
bits in their respective SFRs or control I/O functions via port pins.
The instructions BSET, BCLR, BAND, BOR, BXOR, BMOV, BMOVN explicitly set or
clear specific bits. The instructions BFLDL and BFLDH allow to manipulate up to 8 bits
of a specific byte at one time. The instructions JBC and JNBS implicitly clear or set the
specified bit when the jump is taken. The instructions JB and JNB (also conditional jump
instructions that refer to flags) evaluate the specified bit to determine if the jump is to be
taken.
Note: Bit operations on undefined bit locations will always read a bit value of ‘0’, while
All instructions that manipulate single bits or bit groups internally use a read-modify-write
sequence that accesses the whole word, which contains the specified bit(s).
This method has several consequences:
• Bits can only be modified within the internal address areas, ie. internal RAM and SFRs.
External locations cannot be used with bit instructions.
The upper 256 bytes of the SFR area, the ESFR area and the internal RAM are bit-
addressable (see chapter “Memory Organization”), ie. those register bits located within
the respective sections can be directly manipulated using bit instructions. The other
SFRs must be accessed byte/word wise.
Note: All GPRs are bit-addressable independent of the allocation of the register bank via
• The read-modify-write approach may be critical with hardware-effected bits. In these
cases the hardware may change specific bits while the read-modify-write operation is in
progress, where the writeback would overwrite the new bit value generated by the
hardware. The solution is either the implemented hardware protection (see below) or
realized through special programming (see “Particular Pipeline Effects”).
Protected bits are not changed during the read-modify-write sequence, ie. when
hardware sets eg. an interrupt request flag between the read and the write of the read-
modify-write sequence. The hardware protection logic guarantees that only the intended
bit(s) is/are effected by the write-back operation.
Note: If a conflict occurs between a bit manipulation generated by hardware and an
A summary of the protected bits implemented in the C161U can be found at the end of
chapter “Architectural Overview”.
the write access will not effect the respective bit location.
the context pointer CP. Even GPRs which are allocated to not bit-addressable
RAM locations provide this feature.
intended software access the software access has priority and determines the
final value of the respective bit.
Bit-Handling and Bit-Protection
62
Central Processor Unit
2001-04-19
C161U