SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 152

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
Figure 32
8.3
In the C161U Port 2 is an 2 -bit port. If Port 2 is used for general purpose I/O, the direction
of each line can be configured via the corresponding direction register DP2. Each port
line can be switched into push/pull or open drain mode via the open drain control register
ODP2.
For port pins configured as input (via DP2 or alternate function), an internal pull transistor
is connected to the pad if register P2PUDEN = ’1’, no matter wheter the C161U is in
normal operation mode or in power down mode. Either pulldown transistor or pullup
transistor will be selected via P2PUDSEL.
For port pins configured as output, the internal pull transistors are always disabled. The
output driver is disabled in power down mode unless P2PHEN = ’1’.
After reset, P2PUDEN and P2PUDSEL are set to LOW signal.
B
n
e
n
a
u
s
r
t
l
y = 7...0
Read DP1H.y/DP1L.y
Write DP1H.y/DP1L.y
PORT2
Write P1H.y/P1L.y
Read P1H.y/P1L.y
Block Diagram of a PORT1 Pin
Port Output
Direction
Latch
Latch
MUX
1
0
Alternate
Output
Data
Alternate
Function
Enable
’1’
152
1
1
0
0
MUX
MUX
Clock
Latch
Input
Output
Buffer
MCB02232
Parallel Ports
2001-04-19
C161U
P1H.y
P1L.y

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