SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 377

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

PLL as well as the whole clock system is stopped as in power down state. This implies
- contrary to Idle mode - , that after wakeup the exit of Sleep mode and thus the start of
any CPU operation is normally delayed by the ramp-up time of the clock system
(oscillator, PLL). Only when the PLL clock is locked on configured frequency, the system
clock is started and the following processing is identical to wakeup from Idle mode.
For description of Idle mode and its possibilities of configuration see Chapter 19.1, "Idle
Mode".
Register in Extended Power Management Module
Note: SYSCON1 is a protected register; its security level is automatically set to full write
The power reduction modes Idle and power down are extended by the Infineons C16x
devices newly introduced sleep mode.
19.4.1
The Sleep mode is a new power management function which represents and is equal to
a Power Down mode but with exit/wakeup handling as in Idle mode. Wakeup from Sleep
state is possible with all external interrupts (including alternate sources e.g. from SSC
interface), with NMI and with RTC interrupts. As in Idle mode also PEC requests are
executed in Sleep mode, resulting in an interruption and resumption of Sleep mode. The
watchdog timer is stopped in Sleep mode. The contents of internal RAM and registers
are preserved through the voltage supplied via the VDD pins.
Generally, the external bus and the XBUS are released during Sleep mode if enabled by
the Hold Enable bit HLDEN in the last Program Status Word PSW. If enabled, the signal
HLDA is active as long as the Sleep mode (as well as the Idle or Power Down mode) is
active. Only when the clock is available again after wakeup, the HOLD request signal is
sampled and the HLDA state continued until HOLD is deactivated.
As in Power Down mode, the Sleep mode may also be combined with a running real time
clock RTC. In Sleep mode the oscillators (RTC and selected oscillator optionally), the
PLL as well as the whole clock system is stopped as in Power Down state. This implies,
that after wakeup the exit of Sleep mode normally is delayed by the ramp-up time of the
clock system (oscillator, PLL).
Sleep mode is entered after the standard IDLE instruction (protected 32 bit instruction)
has been executed and the instruction before the IDLE instruction has been completed.
The selection between standard Idle mode and Sleep mode is controlled with the new
register SYSCON1 (see below).
Data Sheet
Register
SYSCON1
protection after execution of EINIT instruction.
Sleep Mode
System configuration control register for sleep management
Description
377
:
Power Reduction Modes
2001-04-19
C161U