SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 135

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
C161U
Interrupt and Trap Functions
add instruction, the pushed IP value represents the address of the instruction after the
instruction following the add instruction.
Undefined Opcode Trap
When the instruction currently decoded by the CPU does not contain a valid C161U
opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined
opcode trap routine. The IP value pushed onto the system stack is the address of the
instruction that caused the trap.
This can be used to emulate unimplemented instructions. The trap service routine can
examine the faulting instruction to decode operands for unimplemented opcodes based
on the stacked IP. In order to resume processing, the stacked IP value must be
incremented by the size of the undefined instruction, which is determined by the user,
before a RETI instruction is executed.
Protection Fault Trap
Whenever one of the special protected instructions is executed where the opcode of that
instruction is not repeated twice in the second word of the instruction and the byte
following the opcode is not the complement of the opcode, the PRTFLT flag in register
TFR is set and the CPU enters the protection fault trap routine. The protected
instructions include DISWDT, EINIT, IDLE, PWRDN, SRST, and SRVWDT. The IP value
pushed onto the system stack for the protection fault trap is the address of the instruction
that caused the trap.
Illegal Word Operand Access Trap
Whenever a word operand read or write access is attempted to an odd byte address, the
ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access
trap routine. The IP value pushed onto the system stack is the address of the instruction
following the one which caused the trap.
Illegal Instruction Access Trap
Whenever a branch is made to an odd byte address, the ILLINA flag in register TFR is
set and the CPU enters the illegal instruction access trap routine. The IP value pushed
onto the system stack is the illegal odd target address of the branch instruction.
Illegal External Bus Access Trap
Whenever the CPU requests an external instruction fetch, data read or data write, and
no external bus configuration has been specified, the ILLBUS flag in register TFR is set
and the CPU enters the illegal bus access trap routine. The IP value pushed onto the
system stack is the address of the instruction following the one which caused the trap.
Data Sheet
135
2001-04-19

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