SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 184

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
byte). Bit WRCFG in register SYSCON selects the operating mode for pins WR and
BHE. The respective byte will be written on both data bus halfs.
When reading bytes from an external 16-bit device, whole words may be read and the
C161U automatically selects the byte to be input and discards the other. However, care
must be taken when reading devices that change state when being read, like FIFOs,
interrupt status registers, etc. In this case individual bytes should be selected using BHE
and A0.
Note: PORT1 gets available for general purpose I/O, when none of the BUSCON
Disable/Enable Control for Pin BHE (BYTDIS)
Bit BYTDIS is provided for controlling the active low Byte High Enable (BHE) pin. The
function of the BHE pin is enabled, if the BYTDIS bit contains a '0'. Otherwise, it is
disabled and the pin can be used as standard I/O pin. The BHE pin is implicitly used by
the External Bus Controller to select one of two byte-organized memory chips, which are
connected to the C161U via a word-wide external data bus. After reset the BHE function
is automatically enabled (BYTDIS = '0'), if a 16-bit data bus is selected during reset,
otherwise it is disabled (BYTDIS=’1’). It may be disabled, if byte access to 16-bit memory
is not required, and the BHE signal is not used.
Segment Address Generation
During external accesses the EBC generates a (programmable) number of address lines
on Port 4, which extend the 16-bit address output on PORT0 or PORT1, and so increase
the accessible address space. The number of segment address lines is selected during
reset and coded in bit field SALSEL in register RP0H (see table below).
Note: The total accessible address space may be increased by accessing several banks
Bus Mode
8-bit
Multiplexed
8-bit
Demultipl.
16-bit
Multiplexed
16-bit
Demultipl.
registers selects a demultiplexed bus mode.
which are distinguished by individual chip select signals.
Transfer Rate (Speed
factor for byte/word/dword
access)
Very low
Low
High
Very high
( 1.5 / 3 / 6 )
( 1 / 2 / 4 )
( 1.5 / 1.5 / 3 )
( 1 / 1 / 2 )
184
System Requirements
Low
(8-bit latch, byte bus)
Very low
(no latch, byte bus)
High
(16-bit latch, word bus)
Low
(no latch, word bus)
External Bus Interface
Free I/O
Lines
P1H, P1L
P0H
P1H, P1L
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2001-04-19
C161U