MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1013

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
Addresses: CAN0_IFLAG2 is 4002_4000h base + 2Ch offset = 4002_402Ch
41.3.13 Interrupt Flags 1 Register (CANx_IFLAG1)
This register defines the flags for 32 Message Buffer interrupts. It contains one interrupt
flag bit per buffer. Each successful transmission or reception sets the corresponding
IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt will be generated. The
interrupt flag must be cleared by writing 1 to it. Writing 0 has no effect.
The BUF7I to BUF5I flags are also used to represent FIFO interrupts when the Rx FIFO
is enabled. When the bit MCR[RFEN] is set the function of the 8 least significant
interrupt flags BUF[7:0]I changes: BUF7I, BUF6I and BUF5I indicate operating
conditions of the FIFO, and BUF4TO0I are reserved.
Before enabling the RFEN, the CPU must service the IFLAG bits asserted in the Rx
FIFO region; see Section "Rx FIFO". Otherwise, these IFLAG bits will mistakenly show
the related MBs now belonging to FIFO as having contents to be serviced. When the
RFEN bit is negated, the FIFO flags must be cleared. The same care must be taken when
an RFFN value is selected extending Rx FIFO filters beyond MB7. For example, when
RFFN is 0x8, the MB0-23 range is occupied by Rx FIFO filters and related IFLAG bits
must be cleared.
Before updating MCR[MAXMB] field, CPU must service the IFLAG1 bits whose MB
value is greater than the MCR[MAXMB] to be updated; otherwise, they will remain set
and be inconsistent with the amount of MBs available.
Freescale Semiconductor, Inc.
Bit
W
R
31
0
BUFHI
31–0
Field
30
0
29
0
28
0
Buffer MB
Each bit flags the corresponding FlexCAN Message Buffer interrupt.
0
1
27
0
The corresponding buffer has no occurrence of successfully completed transmission or reception.
The corresponding buffer has successfully completed transmission or reception.
26
0
25
0
i
Interrupt
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
0
22
0
CANx_IFLAG2 field descriptions
21
0
20
0
19
0
18
0
17
0
BUFHI
16
0
w1c
15
0
Description
14
0
13
0
12
0
11
0
10
0
0
9
0
8
0
7
Chapter 41 CAN (FlexCAN)
0
6
0
5
4
0
0
3
0
2
0
1
1013
0
0