MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 451

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Freescale Semiconductor, Inc.
MAJORELINK
INTHALF
ACTIVE
DONE
DREQ
Field
ESG
7
6
5
4
3
2
Channel Done
This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count
reaches zero; The software clears it, or the hardware when the channel is activated.
NOTE: This bit must be cleared to write the MAJORELINK or ESG bits.
Channel Active
This flag signals the channel is currently in execution. It is set when channel service begins, and the
eDMA clears it as the minor loop completes or if any error condition is detected. This bit resets to zero.
Enable channel-to-channel linking on major loop complete
As the channel completes the major loop, this flag enables the linking to another channel, defined by
MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism
that sets the TCDn_CSR[START] bit of the specified channel.
NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while
0
1
Enable Scatter/Gather Processing
As the channel completes the major loop, this flag enables scatter/gather processing in the current
channel. If enabled, the eDMA engine uses DLASTSGA as a memory pointer to a 0-modulo-32 address
containing a 32-byte data structure loaded as the transfer control descriptor into the local memory.
NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written
0
1
Disable Request
If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current
major iteration count reaches zero.
0
1
Enable an interrupt when major counter is half complete.
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT
register when the current major iteration count reaches the halfway point. Specifically, the comparison
performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
provided to support double-buffered (aka ping-pong) schemes or other types of data movement where the
processor needs an early indication of the transfer’s progress. If BITER is set, do not use INTHALF. Use
INTMAJOR instead.
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at
The channel-to-channel linking is disabled
The channel-to-channel linking is enabled
The current channel’s TCD is normal format.
The current channel’s TCD specifies a scatter gather format. The DLASTSGA field provides a
memory pointer to the next TCD to be loaded into this channel after the major loop completes its
execution.
The channel’s ERQ bit is not affected
The channel’s ERQ bit is cleared when the major loop is complete
the channel defined by these six bits by setting that channel’s TCDn_CSR[START] bit.
the TCDn_CSR[DONE] bit is set.
to while the TCDn_CSR[DONE] bit is set.
DMA_TCDn_CSR field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Chapter 21 Direct Memory Access Controller (eDMA)
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