MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1188

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MK30DN512ZVLK10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Memory map and registers
44.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO)
This register provides the ability to set a programmable threshold for notification of
needing additional transmit data. This register may be read at any time but should only be
written when C2[TE] is not set. Changing the value of the watermark will not clear the
S1[TDRE] flag.
Addresses: UART0_TWFIFO is 4006_A000h base + 13h offset = 4006_A013h
44.3.20 UART FIFO Transmit Count (UARTx_TCFIFO)
This is a read only register that indicates how many datawords are currently in the
transmit buffer/FIFO. It may be read at anytime.
Addresses: UART0_TCFIFO is 4006_A000h base + 14h offset = 4006_A014h
1188
TXWATER
Reset
Field
Reset
Read
7–0
Read
Write
Write
Bit
Bit
UART1_TWFIFO is 4006_B000h base + 13h offset = 4006_B013h
UART2_TWFIFO is 4006_C000h base + 13h offset = 4006_C013h
UART3_TWFIFO is 4006_D000h base + 13h offset = 4006_D013h
UART1_TCFIFO is 4006_B000h base + 14h offset = 4006_B014h
UART2_TCFIFO is 4006_C000h base + 14h offset = 4006_C014h
UART3_TCFIFO is 4006_D000h base + 14h offset = 4006_D014h
Transmit Watermark
When the number of datawords in the transmit FIFO/buffer is equal to or less than the value in this
register field then an interrupt via S1[TDRE] or a DMA request via C5[TDMAS] will be generated as
determined by C5[TDMAS] and C2[TIE] fields. For proper operation the value in the TXWATER field must
be set to be less than the size of the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and
PFIFO[TXFE].
7
0
7
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
0
0
6
6
UARTx_TWFIFO field descriptions
0
0
5
5
0
0
4
4
TXWATER
TXCOUNT
Description
0
0
3
3
0
0
2
2
Freescale Semiconductor, Inc.
0
0
1
1
0
0
0
0

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