MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1301

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Chapter 45 Secured digital host controller (SDHC)
System Address
Crossbar
switch
R/W indication
eSDHC Registers
interface
Error Indication
Master
Logic
Burst Length
Buffer Control
Data Exchange
D
MA
Engine
DMA Request
Figure 45-31. DMA crossbar switch interface block
45.5.2.1 Internal DMA request
If the watermark level requirement is met in data transfer, and the internal DMA is
enabled, the data buffer block sends a DMA request to the crossbar switch interface.
Meanwhile, the external DMA request signal is disabled. The delay in response from the
internal DMA engine depends on the system bus loading and the priority assigned to the
SDHC. The DMA engine does not respond to the request during its burst transfer, but is
ready to serve as soon as the burst is over. The data buffer de-asserts the request once an
access to the buffer is made. Upon access to the buffer by internal DMA, the data buffer
updates its internal buffer pointer, and when the watermark level is satisfied, another
DMA request is sent.
The data transfer is in the block unit, and the subsequent watermark level is always set as
the remaining number of words. For instance, for a multi block data read with each block
size of 31 bytes, and the burst length set to 6 words. After the first burst transfer, if there
are more than 2 words in the buffer (which might contain some data of the next block),
another DMA request read is sent. This is because the remaining number of words to
send for the current block is (31 - 6 * 4) / 4 = 2. The SDHC will read 2 words out of the
buffer, with 7 valid bytes and 1 stuff byte.
45.5.2.2 DMA burst length
Just like a CPU polling access, the DMA burst length for the internal DMA engine can be
from 1 to 16 words. The actual burst length for the DMA depends on the lesser of the
configured burst length or the remaining words of the current block. Take the example in
Internal DMA request
again. The following burst length after 6 words are read will be 2
words, and the next burst length will be 6 words again. This is because the next block
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1301