MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1226

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional description
When the C7816[INIT] bit is set, the receiver will search all received data for the first
valid initial character. All data received which is not a valid initial character will be
ignored and all flags resulting from the invalid data will be blocked from asserting. If the
C7816[ANACK] bit is set, a NACK will be returned for invalid received initial
characters and a RXT interrupt will be generated as programmed.
44.4.7.2 Protocol T = 0
When T = 0 protocol is selected, a relatively complex error detection scheme is used.
Data characters are formatted as illustrated in the following figure. This scheme is also
used for answer to reset and PPS formats.
As with other protocols supported by the UART the data character includes a start bit.
However, in this case there are two stop bits rather than the typical single stop bit. In
addition to a standard even parity check, the receiver has the ability to generate and return
a NACK during the second half of the first stop bit period. The NACK must be at least
one time period (ETU) in length and no more than 2 time periods (ETU) in length. The
transmitter must wait for at least two time units (ETU) after detection of the error signal
before attempting to retransmit the character.
It is assumed that the UART and the device (smartcard) know in advance which device is
receiving and which is transmitting. No special mechanism is supplied by the UART to
control receive and transmit in the mode other than the C2[TE] and C2[RE] bits.
44.4.7.3 Protocol T = 1
When T = 1 protocol is selected the NACK error detection scheme is not used. Rather,
the parity bit is used on a character basis and a CRC or LRC is used on the block basis
(i.e. each group of characters). As such, in this mode the data format allows for a single
stop bit although additional inactive bit periods may be present between the stop bit and
the next start bit. Data characters are formatted as illustrated in the following figure.
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START
START
BIT
BIT
BIT 0
BIT 0
BIT 1
BIT 1
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
ISO 7816 FORMAT WITHOUT PARITY ERROR (T=0)
Figure 44-181. ISO-7816 T = 0 data format
ISO 7816 FORMAT WITH PARITY ERROR (T=0)
BIT 2
BIT 2
BIT 3
BIT 3
BIT 4
BIT 4
BIT 5
BIT 5
BIT 6
BIT 6
BIT 7
BIT 7
PARITY
PARITY
BIT
BIT
STOP
BIT
ERROR
NACK
STOP
BIT
Freescale Semiconductor, Inc.
START
STOP
NEXT
BIT
BIT
START
NEXT
BIT