MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1168

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

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Manufacturer
Quantity
Price
Part Number:
MK30DN512ZVLK10
Manufacturer:
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Quantity:
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Memory map and registers
1168
TCIE
RWU
Field
ILIE
RIE
TIE
RE
TE
7
6
5
4
3
2
1
Transmitter Interrupt or DMA Transfer Enable.
TIE enables the S1[TDRE] flag, to generate interrupt requests or DMA transfer requests, based on the
state of C5[TDMAS].
NOTE: If C2[TIE] and C5[TDMAS] are both set, then TCIE must be cleared, and D[D] must not be
0
1
Transmission Complete Interrupt Enable
TCIE enables the transmission complete flag, S1[TC], to generate interrupt requests.
0
1
Receiver Full Interrupt or DMA Transfer Enable
RIE enables the S1[RDRF] flag, to generate interrupt requests or DMA transfer requests, based on the
state of C5[RDMAS].
0
1
Idle Line Interrupt Enable
ILIE enables the idle line flag, S1[IDLE], to generate interrupt requests, based on the state of
C5[ILDMAS].
0
1
Transmitter Enable
TE enables the UART transmitter.The TE bit can be used to queue an idle preamble by clearing and then
setting the TE bit. When 7816E is set/enabled and C7816[TTYPE] = 1, this bit is automatically cleared
after the requested block has been transmitted. This condition is detected when TL7816[TLEN] = 0 and
four additional characters have been transmitted.
0
1
Receiver Enable
RE enables the UART receiver.
0
1
Receiver Wakeup Control
This bit can be set to place the UART receiver in a standby state. RWU automatically clears when an
RWU event occurs (an IDLE event when C1[WAKE] is clear or an address match when C1[WAKE] is set).
This bit must be cleared when 7816E is set.
TDRE interrupt and DMA transfer requests disabled.
TDRE interrupt or DMA transfer requests enabled.
TC interrupt requests disabled.
TC interrupt requests enabled.
RDRF interrupt and DMA transfer requests disabled.
RDRF interrupt or DMA transfer requests enabled
IDLE interrupt requests disabled.
IDLE interrupt requests enabled.
Transmitter off.
Transmitter on.
Receiver off.
Receiver on.
written outside of servicing of a DMA request.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
UARTx_C2 field descriptions
Table continues on the next page...
Description
Freescale Semiconductor, Inc.

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