MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1295

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

For a read operation, when there are more words in the buffer than the amount set in the
WML register, the internal DMA starts fetching data over the crossbar switch bus. Except
INCR4 and INCR8, the burst type is always INCR mode and the burst length depends on
the shortest of following factors:
Write operation is similar.
Sequential and contiguous access is necessary to ensure the pointer address value is
correct. Random or skipped access is not possible. The byte order, by reset, is little
endian mode. The actually byte order is swapped inside the buffer, according to the
endian mode configured by software, as illustrated in the following diagrams. For a host
write operation, byte order is swapped after data is fetched from the buffer and ready to
send to the SD bus. For a host read operation, byte order is swapped before the data is
stored into the buffer.
Freescale Semiconductor, Inc.
1. Burst length configured in the burst length field of the WML register
2. Watermark level boundary
3. Block size boundary
4. Data boundary configured in the current descriptor (if the ADMA is active)
5. 1 KB address boundary
• External DMA mode:
• Internal DMA mode (includes simple and advanced DMA access's):
• For a read operation, when there are more words received in the buffer than the
• The internal DMA access, either by simple or advanced DMA, is over the
amount set in the RDWML register, a DMA request is sent out to inform the
external DMA to fetch the data. The request will be immediately de-asserted
when there is an access on the DATPORT register. If the number of words in the
buffer after the current burst meets or exceeds RDWML value, then the DMA
request is asserted again. So for instance if there are twice as many words in the
buffer than the RDWML value, there are two successive DMA requests with
only one cycle of de-assertion between. The write operation is similar.
Note the accesses CPU polling mode and external DMA mode both use the IP
bus, and if the external DMA is enable, in both modes an external DMA request
is sent out whenever the buffer is ready.
crossbar switch bus. For internal DMA access mode, the external DMA request
will never be sent out.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 45 Secured digital host controller (SDHC)
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