MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 357

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Reset
18.3.5 Region Descriptor n, Word 1 (MPU_RGD_WORD1)
The second word of the region descriptor defines the 31-modulo-32 byte end address of
the memory region. Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]).
Addresses: 4000_D000h base + 404h offset + (16d × n), where n = 0d to 11d
18.3.6 Region Descriptor n, Word 2 (MPU_RGD_WORD2)
The third word of the region descriptor defines the access control rights of the memory
region. The access control privileges depend on two broad classifications of bus masters:
For the privilege rights of bus masters 0–3, there are three flags associated with this
function:
Freescale Semiconductor, Inc.
Bit
W
R
• Bus masters 0–3 have a 5-bit field defining separate privilege rights for user and
• Bus masters 4–7 are limited to separate read and write permissions.
• Read (r) refers to accessing the referenced memory address using an operand (data)
• Write (w) refers to updating the referenced memory address using a store (data)
• Execute (x) refers to reading the referenced memory address using an instruction
ENDADDR
Reserved
31
0
supervisor mode accesses.
fetch
instruction
fetch
31–5
Field
4–0
30
0
29
0
28
0
End address
Defines the most significant bits of the 31-modulo-32 byte end address of the memory region.
NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR.
This field is reserved.
27
0
26
0
25
0
24
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
23
MPU_RGDn_WORD1 field descriptions
0
22
0
21
0
20
0
ENDADDR
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
12
0
11
Chapter 18 Memory Protection Unit (MPU)
0
10
0
0
9
0
8
0
7
0
6
0
5
4
1
Reserved
1
3
1
2
1
1
357
1
0