MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 160

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Internal clocking requirements
5.5 Internal clocking requirements
The clock dividers are programmed via the SIM module’s CLKDIV registers. Each
divider is programmable from a divide-by-1 through divide-by-16 setting. The following
requirements must be met when configuring the clocks for this device:
160
1. The core and system clock frequencies must be 100 MHz or slower.
External reference
External reference
Internal reference
I2S master clock
RTC_CLKOUT
(OSCERCLK)
(MCGIRCLK)
TRACE clock
(ERCLK32K)
Clock name
SDHC clock
32kHz
LPO
30-40 kHz or 2 MHz
Up to 50 MHz
(bypass),
30-40 kHz, or
4-32 MHz (crystal)
30-40 kHz
1 Hz
1 kHz
Up to 50 MHz
Up to 50 MHz
Up to 100 MHz
Run mode
clock frequency
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 5-1. Clock Summary (continued)
2 MHz only
Up to 4 MHz (bypass),
30-40 kHz (low-range
crystal) or
Up to 4 MHz (high-
range crystal)
30-40 kHz
1 Hz
1 kHz
N/A
N/A
Up to 2 MHz
VLPR mode
clock frequency
MCG
System OSC
System OSC or RTC
OSC depending on
SIM_SOPT1[OSC32K
SEL]
RTC clock
PMC
System clock,
MCGPLLCLK, or
MCGFLLCLK with
fractional clock divider,
OSCERCLK, or
I2S_CLKIN
System clock,
MCGPLLCLK/
MCGFLLCLK, or
OSCERCLK
System clock or
MCGOUTCLK
Clock source
Freescale Semiconductor, Inc.
MCG_C1[IRCLKEN]
cleared,
Stop mode and
MCG_C1[IREFSTEN]
cleared, or
VLPS/LLS/VLLS mode
System OSC's
OSC_CR[ERCLKEN]
cleared, or
Stop mode and
OSC_CR[EREFSTEN]
cleared
System OSC's
OSC_CR[ERCLKEN]
cleared or
RTC's RTC_CR[OSCE]
cleared
Clock is disabled in
LLS and VLLSx modes
Available in all power
modes
I
SDHC is disabled
Trace is disabled
Clock is disabled
when…
2
S is disabled