MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 907

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

When a rising edge occurs in the channel (n) input signal, the FTM counter value is
captured into channel (n) capture buffer. The channel (n) capture buffer value is
transferred to C(n)V register when a falling edge occurs in the channel (n) input signal.
C(n)V register has the FTM counter value when the previous rising edge occurred, and
the channel (n) capture buffer has the FTM counter value when the last rising edge
occurred.
When a falling edge occurs in the channel (n) input signal, the FTM counter value is
captured into channel (n+1) capture buffer. The channel (n+1) capture buffer value is
transferred to C(n+1)V register when the C(n)V register is read.
In the following figure, the read of C(n)V returns the FTM counter value when the event
1 occurred and the read of C(n+1)V returns the FTM counter value when the event 2
occurred.
C(n)V register must be read prior to C(n+1)V register in dual edge capture one-shot and
continuous modes for the read coherency mechanism works properly.
36.4.25 Quadrature Decoder Mode
The quadrature decoder mode is selected if (FTMEN = 1) and (QUADEN = 1). The
quadrature decoder mode uses the input signals phase A and B to control the FTM
counter increment and decrement. The following figure shows the quadrature decoder
block diagram.
Each one of input signals phase A and B has a filter that is equivalent to the filter used in
the channels input
PHAFLTREN bit and this filter’s value is defined by CH0FVAL[3:0] bits
Freescale Semiconductor, Inc.
channel (n) input
channel (n+1)
capture buffer
capture buffer
(after the filter
channel input)
FTM counter
channel (n)
C(n+1)V
C(n)V
Figure 36-249. Dual Edge Capture Mode Read Coherency Mechanism
(Filter for Input Capture
event 1
1
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
event 2
1
2
event 3
1
3
2
read C(n)V
event 4
4
3
Mode). The phase A input filter is enabled by
event 5
3
4
5
event 6
6
5
2
read C(n+1)V
event 7
5
6
7
Chapter 36 FlexTimer (FTM)
event 8
7
8
event 9
9
7
8
9
907