MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1065

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Soft reset is synchronous and has to follow an internal request/acknowledge procedure
across clock domains. Therefore, it may take some time to fully propagate its effects. The
SOFT_RST bit remains asserted while soft reset is pending, so software can poll this bit
to know when the reset has completed. Also, soft reset can not be applied while clocks
are shut down in any of the low power modes. The low power mode should be exited and
the clocks resumed before applying soft reset.
The clock source (CLK_SRC bit) should be selected while the module is in Disable
Mode. After the clock source is selected and the module is enabled (MDIS bit negated),
FlexCAN automatically goes to Freeze Mode. In Freeze Mode, FlexCAN is un-
synchronized to the CAN bus, the HALT and FRZ bits in MCR Register are set, the
internal state machines are disabled and the FRZ_ACK and NOT_RDY bits in the MCR
Register are set. The Tx pin is in recessive state and FlexCAN does not initiate any
transmission or reception of CAN frames. Note that the Message Buffers and the Rx
Individual Mask Registers are not affected by reset, so they are not automatically
initialized.
For any configuration change/initialization it is required that FlexCAN is put into Freeze
Mode (see
the FlexCAN module:
Freescale Semiconductor, Inc.
• Initialize the Module Configuration Register
• Initialize the Control Register
• Initialize the Message Buffers
• Enable the individual filtering per MB and reception queue features by setting
• Enable the warning interrupts by setting the WRN_EN bit
• If required, disable frame self reception by setting the SRX_DIS bit
• Enable the Rx FIFO by setting the RFEN bit
• Enable the abort mechanism by setting the AEN bit
• Enable the local priority feature by setting the LPRIO_EN bit
• Determine the bit timing parameters: PROPSEG, PSEG1, PSEG2, RJW
• Determine the bit rate by programming the PRESDIV field
• Determine the internal arbitration mode (LBUF bit)
• The Control and Status word of all Message Buffers must be initialized
the IRMQ bit
Freeze
Mode). The following is a generic initialization sequence applicable to
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 41 CAN (FlexCAN)
1065