MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 419

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MK30DN512ZVLK10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor, Inc.
Reserved
Reserved
EMLM
EDBG
ERCA
HALT
15–8
HOE
Field
ECX
CLM
16
7
6
5
4
3
2
1
0
1
Error Cancel Transfer
0
1
This read-only field is reserved and always has the value zero.
Enable Minor Loop Mapping
0
1
Continuous Link Mode
0
1
Halt DMA Operations
0
1
Halt On Error
0
1
This read-only field is reserved and always has the value zero.
Enable Round Robin Channel Arbitration
0
1
Enable Debug
Normal operation
Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
the cancel has been honored. This cancel retires the channel normally as if the minor loop was
completed.
Normal operation
Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
force the minor loop to finish. The cancel takes effect after the last write of the current read/write
sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer,
ECX treats the cancel as an error condition, thus updating the ES register and generating an optional
error interrupt.
Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES
field. The individual enable fields allow the minor loop offset to be applied to the source address, the
destination address, or both. The NBYTES field is reduced when either offset is enabled.
A minor loop channel link made to itself goes through channel arbitration before being activated
again.
A minor loop channel link made to itself does not go through channel arbitration before being
activated again. Upon minor loop completion, the channel activates again if that channel has a minor
loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets
and restarts the next minor loop.
Normal operation
Stall the start of any new channels. Executing channels are allowed to complete. Channel execution
resumes when this bit is cleared.
Normal operation
Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT
bit is cleared.
Fixed priority arbitration is used for channel selection.
Round robin arbitration is used for channel selection.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
DMA_CR field descriptions (continued)
Table continues on the next page...
Description
Chapter 21 Direct Memory Access Controller (eDMA)
419

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