MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 377

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MK30DN512ZVLK10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor, Inc.
Reserved
Reserved
WP1
WP2
Field
SP1
SP2
TP1
TP2
27
26
25
24
23
22
21
20
This read-only field is reserved and always has the value zero.
Supervisor protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
Write protect
Determines whether the peripheral allows write accesss. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0
1
Trusted protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
This read-only field is reserved and always has the value zero.
Supervisor protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
Write protect
Determines whether the peripheral allows write accesss. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0
1
Trusted protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
This peripheral allows write accesses.
This peripheral is write protected.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
This peripheral allows write accesses.
This peripheral is write protected.
AIPSx_PACRn field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table continues on the next page...
Description
Chapter 19 Peripheral Bridge (AIPS-Lite)
377

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