MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 1097

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Chapter 42 SPI (DSPI)
42.4.2.1 Master Mode
In SPI master mode the DSPI initiates the serial transfers by controlling the Serial
Communications Clock (SCK) and the Peripheral Chip Select (PCS) signals. The SPI
command field in the executing TX FIFO entry determines which CTAR registers will be
used to set the transfer attributes and which PCS signals to assert. The command field
also contains various bits that help with queue management and transfer protocol. See
DSPI PUSH TX FIFO Register (PUSHR) for details on the SPI command fields. The
data field in the executing TX FIFO entry is loaded into the shift register and shifted out
on the Serial Out (SOUT) pin. In SPI master mode, each SPI frame to be transmitted has
a command associated with it allowing for transfer attribute control on a frame by frame
basis.
42.4.2.2 Slave Mode
In SPI slave mode the DSPI responds to transfers initiated by a SPI bus master. The DSPI
does not initiate transfers. Certain transfer attributes such as clock polarity, clock phase
and frame size must be set for successful communication with a SPI master. The SPI
slave mode transfer attributes are set in the CTAR0. The data is shifted out with MSB
first. Shifting out of LSB is not supported in this mode.
42.4.2.3 FIFO Disable Operation
The FIFO disable mechanisms allow SPI transfers without using the TX FIFO or RX
FIFO. The DSPI operates as a double-buffered simplified SPI when the FIFOs are
disabled. The FIFOs are disabled separately; setting the MCR[DIS_TXF] bit disables the
TX FIFO, and setting the MCR[DIS_RXF] bit disables the RX FIFO.
The FIFO Disable mechanisms are transparent to the user and to host software; Transmit
data and commands are written to the PUSHR and received data is read from the POPR.
When the TX FIFO is disabled the TFFF, TFUF and TXCTR fields in SR behave as if
there is a one-entry FIFO but the contents of the TXFR registers and TXNXTPTR are
undefined. Likewise, when the RX FIFO is disabled, the RFDF, RFOF and RXCTR
fields in the SR behave as if there is a one-entry FIFO, but the contents of the RXFR
registers and POPNXTPTR are undefined.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1097